1. Field of the Invention
The present invention generally relates to general purpose digital data processing systems and more particularly relates to such systems that employ a common bus architecture.
2. Description of the Prior Art
In many general purpose, stored program, digital computers, it is desirable to have at least one shared resource contained therein. Each of the shared resources may be designed to service a number of user. In the context of the present invention, the shared resource may comprise a common bus. The common bus may be connected to a number of processors or the like such that communication between the processors can be made over the common bus.
A problem with using a common bus architecture is that the common bus may reduce the band pass of a system if not carefully used and designed. One reason for this is that only one of the users may be granted access to the common bus at any given time. That is, the users must "share" the resource.
One method for increasing the overall band pass of a common bus architecture is to utilize a priority scheme. Often, one or more of the processors that is connected to the common bus has a greater need to access the common bus than other processors connected thereto. For example, one of the processors may be in the critical path of the computer system. Priority schemes attempt to grant access to the processor that is in the critical path of the computer system over all other processors.
Although a priority scheme may increase the band pass of a given computer system, an underlying problem with the common bus approach still remains. That is, certain users within the computer system may operate at a slower rate than the other users and therefore the slower users may limit the band pass of the computer system. This may occur despite having a priority system implemented therein. One situation where this may occur is when the data format of a "sending" user may not be in an optimum format for use by a "receiving" user. For example, a sending user may impose data having a single precision data format where the receiving user may require a double precision data format or visa-versa. When this occurs, the receiving user may have to reformat the data before performing arithmetic operations thereon, thereby limiting the band pass of the receiving user. Accordingly, the data formatting function may be very time critical, and must be performed at the highest rate possible while maintaining accuracy.
A proposed solution to this problem is addressed in U.S. Pat. No. 4,595,911, issued on Jun. 17, 1986, to Kregness et al. Kregness et al. suggests employing dedicated circuitry to perform the reformatting function. The dedicated circuitry includes a number of programmable ranks of multiplexers for reformatting the data from a programmable selected first format to a programmable selected second formats. However, Kregness et al. only contemplates reformatting the data to increase the speed of a corresponding arithmetic operation. Also, Kregness et al. only suggests "reformatting" data wherein both the input data and the output data have a common word width.
For shorthand purposes only, the present disclosure refers to an interface with a "common bus". However, it is recognized that the "bus" may have a number of components (such as a memory device) coupled thereto. Therefore, what is really disclosed is an interface with a component which is coupled to the bus.
Another situation where certain users within a computer system may limit the band pass of the computer system is when a plurality of high speed users require access to a slower shared resource. An example of this is when a number of high speed processors require access to a slower memory device. High speed processors are typically pipelined or otherwise designed to require little processing between registers, thereby allowing a high clock rate and high throughput. Memory devices, on the other hand, typically must perform a substantial amount of processing during each memory access. For example, for a read operation, a Random Access Memory (RAM) must typically decode the address lines, precharge the bit lines, wait for the memory cells to discharge the bit lines into a corresponding state, sense the resulting state of the bit lines, and output the data. For a write operation, a RAM must typically decode the address lines, precharge the bit lines, force the bit lines into a state that is consistent with the data inputs of the RAM, and wait for a predetermined "write" time to ensure the corresponding memory cells have been written to the proper state.
Because of this inherent incompatibility between high speed processors and memory devices, a system that requires a memory device such as a RAM to service high speed processors may be problematic and limit the band pass of the computer system. This problem is exacerbated when a number of high speed processors are coupled to the memory device over a common bus wherein the memory device must service all of the high speed processors. In this situation, the memory device may be in the critical path of the computer system every time any of the high speed processors access the memory.
Another problem that may occur in system utilizing a common bus is that each processor may employ a different width data word. That is, one processor may only require an eight bit data word while another processor may require a sixteen or thirty-two bit data word. This may create problems when the respective processors utilize a common memory device. One solution to this problem is to provide a memory that has a data word width that is sufficient to accommodate the widest data word that is coupled to the common bus. However, this solution has several disadvantages. One disadvantage is that if a processor requiring an eight bit data word writes into a memory location having a sixteen bit data word width, eight of the sixteen bits at that memory location are squandered. Further, each access to the memory device by any one of the processors may require the processor to wait one full memory cycle, which may be substantially longer than the processors clock cycle.
Yet another problem that may occur as a result of having processors that utilize different data word widths is that the processors may not be able to effectively communicate between one another. That is, one processor that has an eight bit data word may need to communicate with a processors that has a thirty-two bit data word. One solution to this problem is to provide the eight bit data word from a first processor into the least significant eight bits of the thirty-two bit data word of a second processor. Similarly, the most significant bits of the thirty-two bit data word of the second processor may be provided to the eight bit data word of the first processor wherein the remaining twenty-four bits of the thirty-two bit data word are discarded. These solutions are simple but very limiting in their application.